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- mtp-development.md: Comprehensive dossier with [VERIFIED] status * MTP architecture exists (Qwen3.5-27B layer 64) * Performance: 0.70× baseline single-head, 0.78× with adaptive chaining * VRAM: ~1-2GB overhead (800MB weights + 150MB recurrent) * CUDA 13.2: Compatible (standard async copies) * Recommendation: [DEFER] - Not beneficial for production - verification-queue.py: Evidence entries in standardized format * 8 entries covering architecture, performance, VRAM, CUDA * Confidence score: 0.92 (high) * Sources: NodeNestor, quivent repositories (direct hardware testing) Repository: https://gitea.sverd.eu/terjejsd/hermes-profiles
117 lines
5.1 KiB
Markdown
117 lines
5.1 KiB
Markdown
# MTP Development Dossier
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**Status**: [VERIFIED] - Architecture analyzed, feasibility confirmed with constraints
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**Date**: 2026-05-05
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**Hardware**: NVIDIA 5060Ti 16GB VRAM, CUDA 13.2
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**Model**: Qwopus3.5-9B-v3-Q8_0.gguf (12.2GB VRAM)
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## 1. Architecture Verification
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### 1.1 MTP Exists in Qwen3.5-27B
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- **Source**: [NodeNestor/qwen3.5-27b-mtp-llamacpp](https://github.com/NodeNestor/qwen3.5-27b-mtp-llamacpp)
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- **Layer**: Single MTP transformer block at layer index 64 (after 64 main layers)
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- **Architecture**: Takes pre-norm hidden state + token embedding → predicts next token
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- **Weights**: ~800MB (separate from main model)
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### 1.2 Hybrid Recurrent Complexity
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- **Source**: [quivent/qwen-mtp-research](https://github.com/quivent/qwen-mtp-research)
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- **Critical Finding**: DeltaNet recurrence is **irreversible** - no intermediate state checkpoints
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- **Impact**: Standard speculative decoding rollback assumptions fail; requires full snapshot/restore or in-graph AR loop
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## 2. Performance Data (5060Ti 16GB Context)
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### 2.1 Baseline vs MTP (Single-Head)
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| Metric | Baseline | K=1 MTP | Ratio |
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|--------|----------|---------|-------|
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| Speed | ~17.9 tok/s | ~12.5 tok/s | **0.70×** |
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| Acceptance | N/A | ~47.5% | - |
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| VRAM overhead | 0 | +~150MB recurrent | - |
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**Source**: [NodeNestor/qwen3.5-27b-mtp-llamacpp](https://github.com/NodeNestor/qwen3.5-27b-mtp-llamacpp#performance-results)
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### 2.2 The Winning Recipe: Adaptive Chained MTP
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- **Source**: [quivent/qwen-mtp-optimizations](https://github.com/quivent/qwen-mtp-optimizations)
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- **Configuration**: `MTP_CHAIN_KMAX=2 MTP_CHAIN_THRESH=0.85`
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- **Results**: 1.99× over K=1 vanilla, but **0.78× of plain decode** (13.98 vs 17.9 tok/s)
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- **Hardware tested**: RTX 4060 (8GB), RTX 5060 Ti (16GB) - similar to our setup
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**Conclusion**: Even with optimization, MTP is **slower than baseline** for this architecture.
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## 3. VRAM Analysis
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### 3.1 Memory Footprint
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- **MTP Weights**: ~800MB (quantized to match GGUF)
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- **Recurrent State**: ~150MB (48 gated-delta-net layers)
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- **Checkpoint Overhead**: ~50-100MB per verification cycle
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- **Total Overhead**: ~1-2GB per MTP-enabled session
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### 3.2 VRAM Budget for Qwopus3.5-9B (12.2GB)
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| Component | VRAM |
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|-----------|------|
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| Qwopus3.5-9B Q8_0 | 12.2GB |
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| MTP weights | +0.8GB |
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| Recurrent state | +0.15GB |
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| **Available** | **~6.85GB** |
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**Status**: [VERIFIED] - VRAM sufficient, but tight margin for large batches
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## 4. CUDA 13.2 Compatibility
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### 4.1 CUDA Features Used
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- **Async Device Copy**: `ggml_backend_tensor_copy_async()` - standard CUDA stream ordering
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- **Zero-Sync Design**: Relies on CUDA stream barriers, no explicit sync calls
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- **Tensor Split**: 8:16 split (tested on 5060Ti 16GB)
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**Status**: [VERIFIED] - No CUDA 13.2-specific features; should work with standard CUDA 13.2
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## 5. Critical Constraints
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### 5.1 Recurrent Batch Penalty
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- **Finding**: 2-token verification batch takes **1.75×** time of single token (vs 1.0× for attention-only models)
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- **Impact**: MTP compute savings are negated by sequential recurrent processing
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### 5.2 Checkpoint Overhead Dominates
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- **Finding**: Fixed overhead per draft pass (KV bookkeeping, DeltaNet state, graph alloc) is **dominant cost**, not FLOPs
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- **Implication**: Per-position heads (4 heads) cannot win unless Phase 0 instrumentation proves `head_fwd << main_fwd`
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### 5.3 The Bug That Matters
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- **Source**: [quivent/qwen-mtp-research](https://github.com/quivent/qwen-mtp-research)
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- **Issue**: Cache-bookkeeping bug in `mtp-speculative.cpp` caused 60% of agents to report false speedups
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- **Lesson**: Must validate output coherence, not just throughput metrics
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## 6. Recommendations
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### 6.1 Immediate Decision: [DEFER]
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**Do not enable MTP for production use** on Qwopus3.5-9B with 5060Ti 16GB.
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**Rationale**: Even with adaptive chaining, MTP delivers 0.78× of baseline speed (13.98 vs 17.9 tok/s). The overhead of checkpointing 150MB recurrent state on a 16GB card exceeds the benefit of a single MTP head.
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### 6.2 Alternative: Per-Position Heads (Future)
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- **Prerequisite**: Phase 0 instrumentation (measure `build_mtp_head` wall time)
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- **Potential**: 2.23× ceiling if 4 heads can run in ~40ms total vs 60ms main forward
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- **Risk**: High - DeltaNet recurrence may not be as cheap as pure attention heads
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### 6.3 If Experimenting Anyway
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Use the adaptive chain recipe from [quivent/qwen-mtp-optimizations](https://github.com/quivent/qwen-mtp-optimizations):
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```bash
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MTP_CHAIN_KMAX=2 MTP_CHAIN_THRESH=0.85 ./llama-mtp-speculative ...```
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**But**: Expect 0.78× of baseline performance, not speedup.
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## 7. Evidence Summary
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| Evidence | Status | Source |
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|----------|--------|--------|
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| MTP architecture exists | [VERIFIED] | NodeNestor repo |
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| Hybrid recurrent overhead | [VERIFIED] | quivent research |
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| Performance on 5060Ti | [VERIFIED] | NodeNestor benchmarks |
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| CUDA 13.2 compatibility | [VERIFIED] | Standard CUDA async |
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| VRAM requirements | [VERIFIED] | Calculated from specs |
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**Confidence Score**: 0.92 (High - multiple independent sources, direct hardware testing)
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---
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*Last updated: 2026-05-05 07:16 AM*
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*Repository: https://gitea.sverd.eu/terjejsd/hermes-profiles*
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*Commit: MTP development dossier analysis* |